aes is in design. Values marked TARGET are design goals, not measured data.
01Simplified block diagram
02What changes from ASR34
- Converters: new 12-bit, 100 MSPS converters replace the discontinued AD9862
- Processing: aez20 Zynq-7020 replaces both the USB controller and the separate FPGA
- Bandwidth: full rate processed on board; up to 80 MHz in wideband mode, 4 × 40 MHz in DF mode
- Host link: single-pair Gigabit Ethernet with power on one cable, USB-C for service
- Standalone operation: detection and direction finding on the device, results to the network
- Same aex daughterboard interface as ASR34
03Specifications
| Parameter | Value |
|---|---|
| Converters | 4 × 12-bit ADC, 100 MSPS; 4 × DAC |
| Processing | aez20: dual Cortex-A9 + FPGA (XC7Z020) |
| RF | 2 × aex: 1 MHz – 6 GHz, 4 coherent RX |
| Bandwidth | 4 × 40 MHz (DF) or 2 × 80 MHz (wideband)TARGET |
| Network | 1000BASE-T1 single-pair Ethernet with powerTARGET |
| Service port | USB-C (USB 2.0, power delivery) |
| Variants | ASR35; ASR36 to be announced |
04Contact
Early access and integration enquiries: info@a2e.tech
aes is a product of A2E Tech Limited (aegisel), Edinburgh, UK.
Specifications subject to change without notice. Rev 0.1, 7 October 2026.